This application claims the benefit of Korean Patent Application No. 10-2004-0086539, filed on Oct. 28, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Disclosure
Embodiments of the present disclosure may include a non-volatile semiconductor memory device, and more particularly, a phase change memory device and a method of operating the same.
2. Description of the Related Art
Semiconductor memory devices are categorized into volatile memory devices and non-volatile memory (NVM) devices. Volatile memory devices, such as DRAMs, are used in, for example, computers to store and process data in a short time when power is supplied.
However, as demand for mobile phones and digital cameras increases, the demand for non-volatile memory devices increases due to their advantages over DRAMs. For example, non-volatile devices can process data in a short time, and store date even when power is no longer supplied.
Examples of non-volatile memory devices include flash memory devices, which include a stacked gate to retain electric charges. In such flash memory devices, electric charges are stored in or removed from a floating gate by tunneling via an insulator or by hot-carrier injection. However, when flash memory devices are repeatedly used, insulating characteristics of the insulator for tunneling deteriorate. As a result, the lifetime of a flash memory decreases.
In response to the above-mentioned problem, non-volatile memory devices have been developed to replace flash memory devices having stacked gates. For example, phase change memories or phase change RAMs (PRAMs) in which a change in resistivity due to phase change is used has been developed. A conventional phase change memory will now be described with reference to drawings.
FIG. 1 is an equivalent circuit diagram of a portion of a cell array of a conventional phase change memory device.
Referring to FIG. 1, each unit cell of the conventional phase change memory device includes an access transistor 10 and a phase change resistor 12. The access transistors 10 are connected to bit lines BL1 and BL2. Therefore, when the access transistors 10 are turned on, a working voltage is applied to the phase change resistors 12 via the bit lines BL1 and BL2.
Signals received by gates of the access transistors 10 from the word lines WL1 and WL2 turn the access transistors 10 on and off. As is shown in FIG. 1, the unit cells are arranged in a matrix composed of rows and columns. In this case, the word lines WL1 and WL2 form rows, and the bit lines BL1 and BL2 form columns. Therefore, a unit cell can be selected by selecting a word line and a bit line. Further, programming, reading, or erasing can be performed in the selected unit cell.
FIG. 2 is a graph illustrating a method of operating a conventional phase change memory device.
Referring to FIG. 2, a heat treatment 17 for programming a phase change memory device and a heat treatment 15 for erasing the phase change memory device are illustrated. When the phase change resistor 12 is heated to a temperature greater than its melting point (Tm) in a predetermined amount of time T1 and then is cooled down in a short time, the phase change resistor 12 transforms into an amorphous state. When the phase change resistor 12 is heated to a temperature between a crystallization temperature Tc and a meting point Tm in a predetermined amount of time T1, is maintained at the same in a predetermined amount of time T2, and then cooled down, the phase change resistor 12 is crystallized. In a conventional phase change memory device, the phase change resistor 12 is resistively heated by providing a current to both ends of the phase change resistor 12. Therefore, heat required for phase change is obtained.
The resistivity of the phase change resistor 12 varies according to whether the phase change resistor 12 is in a crystalline state or an amorphous state. In detail, the phase change resistor 12 has greater resistivity when it is in an amorphous state than when it is in a crystalline state. Therefore, data can be read in logic “0” or logic “1” by detecting current flowing through the phase change resistor 12 when a predetermined voltage applied. That is, data can be stored in a digital form, that is, logic “0” or logic “1” without the accumulation of electric charges, which is required for DRAMs or flash memory devices.
However, as is shown in FIG. 2, the erasing and programming of a phase change memory device require a high current for heating at a high temperature. Particularly, quick operation requires quick heating. Due to such a time limit, a high current must be provided to the phase change resistor 12 in a short time.
To increase the current flown to the phase change resistor 12, a high voltage must be applied to the bit lines BL1 and BL2. However, when the voltage of the bit lines BL1 and BL2 increases, a gate length of the access transistor 10 must also be increased to prevent problems, such as punch-through. Therefore, a conventional phase change memory device cannot be easily integrated due to the difficulty in reducing the size of the access transistor 10.